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Wakum Mata!
Politcally Incorrect Musings
WOOT! 
22nd-Mar-2006 02:19 pm
southpark
I just ran my first successful VHDL simulation!

Yea me!


My code for the device:


-- Lessons from Designer's Guide to VHDL, 2nd ed.
-- Chapter 1, exercise 8
-- Write an entity declaration and a behavioral architecture body for a two-
-- input multiplexer, with input ports a, b, and sel and an output port z. If the sel
-- input is '0', the value of a should be copied to z, otherwise the value of b should
-- be copied to z. Write a test bench for the multiplexer model, and test it using a
-- VHDL simulator.

entity mux2 is
    port( a, b, sel : in bit;
	z : out bit);
end entity mux2;

architecture behav of mux2 is
begin
    latch_behavior : process (a, b, sel) is
    begin
	if sel = '0' then
	    z <= a;
	end if;
	if sel = '1' then
	    z <= b;
    end if;
--    wait;
    end process latch_behavior;
end architecture behav;





My code for the testbench:


-- Lessons from Designer's Guide to VHDL, 2nd ed.
-- Chapter 1, exercise 8
-- Write an entity declaration and a behavioral architecture body for a two-
-- input multiplexer, with input ports a, b, and sel and an output port z. If the sel
-- input is '0', the value of a should be copied to z, otherwise the value of b should
-- be copied to z. Write a test bench for the multiplexer model, and test it using a
-- VHDL simulator.

entity mux2_tb is
end entity mux2_tb;

architecture test_mux2 of mux2_tb is
	signal a, b, sel, z : bit;
begin
	dut : entity work.mux2(behav)
		port map (a, b, sel, z);
	stimulus : process is
	begin
		a <= '0'; b <= '0'; sel <= '0';
		wait for 20 ns;
		b <= '1';
		wait for 20 ns;
		sel <= '1';
		wait for 20 ns;
		sel <= '0';
		wait for 20 ns;
		a <= '1';
		wait for 20 ns;
		b <= '0';
		wait for 20 ns;
		sel <= '1';
		wait for 20 ns;
		wait;
	end process stimulus;
end architecture test_mux2;



It was a little tricky as I originally forgot to add a wait statement and its sensitivity list to the device architecture. Fortunately, Symphony EDA's Sonata Simili 3.0 is pretty intelligent as it complained about not having the wait statement and told me the possible result. When I ran the simulation the first time, only my input signals changed. I played with the simulator thinking I chose the wrong toplevel. I didn't. I just didn't have any sensitivity list on my wait statement so the process in the device's behavioral architecture just hung and didn't do anything. Fixed that and it all works.

My new book The Designer's Guide to VHDL by Peter J. Ashenden, is just awesome. I have tried to write VHDL code and simulate it before when studying VHDL A Starter's Guide by Sudhakar Yalamanchili. That book just sucks. A total and utter waste of $46 US. None of the code I wrote based on reading that book did anything other than compile.
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