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Wakum Mata!
Politcally Incorrect Musings
I'm on a VHDL roll!!! 
22nd-Mar-2006 06:05 pm
southpark
Yeah baby!

I just got that full adder from the sucky book working! You can tell from the code that I had no clue what I was doing before. But now I do (have a clue at least) thanks to the good book and I made that summabitch work! WOOT!


Full adder VHDL code:

-- 
-- full_adder.vhd
-- 
-- Based off full adder from "VHDL A Starters Guide" by Sudhakar Yalamanchili.
-- BTW, that book sucks. Don't buy it.
--
-- Date  : Jan 31, 2006
-- Author: mmh
-- 
-- Description:
--
-- This module implements a simple full adder (the unit under test).
-- see page 38 of VHDL: A Starter's Guide  
-- 
-- Revision History: [let's just not go there]
-- 
library IEEE;
use IEEE.std_logic_1164.all;

entity full_adder is
	port (C_in: in std_ulogic;
		In_bus: in std_ulogic_vector (1 downto 0);
		sum, c_out: out std_ulogic);
end entity full_adder;

architecture dataflow of full_adder is
	signal s1, s2, s3 : std_logic;
	constant gate_delay : time := 5 ns;
	begin
		L1:s1 <= (In_bus(0) xor In_bus(1)) after gate_delay;
		L2:s2 <= (C_in and s1) after gate_delay;
		L3:s3 <= (In_bus(0) and In_bus(1)) after gate_delay;
		L4:sum <= (C_in and s1) after gate_delay;
		L5:c_out <= (s2 or s3) after gate_delay;
end architecture dataflow;











-- WARNING: Your VHDL Code has got an EMPTY ENTITY



-- File Name : full_adder_tb.vhdl



-- This testbench was automatically generated
-- http://www.vhdl-online.de/
-- ( and I modified the Hell out of it )

-- Filename          : tb_tmp.vhd
-- Modelname         : TB_FULL_ADDERFULL_ADDER
-- Title             :
-- Purpose           :
-- Author(s)         : root
-- Comment           :
-- Assumptions       :
-- Limitations       :
-- Known errors      :
-- Specification ref :
-- ------------------------------------------------------------------------
-- Modification history: [just ignore this... too many edits to count]
-- ------------------------------------------------------------------------
-- Version  | Author | Date       | Changes made
-- ------------------------------------------------------------------------
-- 1.0      | root | 01.02.2006 | inital version


library IEEE;
use IEEE.std_logic_1164.all;

entity TB_FULL_ADDERFULL_ADDER is
end TB_FULL_ADDERFULL_ADDER;

architecture BEH of TB_FULL_ADDERFULL_ADDER is

--	signal C_in, In_bus0, In_bus1, sum, c_out : bit;

   COMPONENT full_adder IS
	port (C_in: in std_ulogic;
		In_bus: in std_ulogic_vector (1 downto 0);
		sum, c_out: out std_ulogic);
   END COMPONENT ;

   constant PERIOD : time := 10 ns;

   signal W_C_IN : std_ulogic ;
   signal W_IN_BUS : std_ulogic_vector ( 1 downto 0 );
   signal W_SUM, W_C_OUT  : std_ulogic ;
--   SIGNAL done		: BOOLEAN := FALSE ;
--   SHARED VARIABLE Cycle : NATURAL := 0 ;

begin

   DUT : full_adder
      port map(C_IN	=> W_C_IN,
               IN_BUS   => W_IN_BUS,
               SUM      => W_SUM,
               C_OUT    => W_C_OUT);
   testbench: PROCESS IS
   BEGIN
	W_C_IN     <= '0',
                    '1' after period,
                    '0' after period * 3,
                    '1' after period * 5,
                    '0' after period * 7,
                   '1' after period * 9,
                    '0' after period * 11,
                    '1' after period * 13,
                    '0' after period * 15;
        W_IN_BUS   <= "00",
      		    "01" after period * 2,
      		    "10" after period * 4,
      		    "11" after period * 6,
      		    "00" after period * 8;
	wait;
   end process;
   
--    ClkProcess: PROCESS(W_C_OUT) IS
--    BEGIN
--    	IF  (NOT done) THEN
--	    IF (W_C_OUT = '1') THEN
--		Cycle := Cycle + 1 ;
--	    END IF ;
--	    W_C_IN <= NOT W_C_OUT after period / 2 ;
--	    IF (Cycle > 10) THEN
--	    	done <= TRUE ;
--	    END IF ; 
--	END IF ;
--    END PROCESS ;
-- Like duh... there is NO CLOCK!!!!
-- [smacks forehead] "C_in" and "C_out" are carry signals!! 

end architecture BEH;


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